Filed under
fpga
Follow a thread through projects and writing.
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An FPGA IoT gateway with a custom AES core
From a VHDL AES-128 core to live sensor readings: a Nexys A7 gateway with bare-metal C firmware, Ethernet telemetry, and a Python controller.
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A moving average, built in hardware
Inside a VHDL signal filter: the four-sample datapath, ROM handshake, reset controllers, and simulation checks on a DE2-115 FPGA.